Devices with high capacitor surface-density and reduced spurious noise have been of major concern in the recent years for applications like power-supply decoupling. Indeed, many applications such as cellular phones, laptop computers, etc., are embedding multicore processors, with very high operation frequencies, that need embeddable and ultra-fast stepping power supplies, with variable and extremely stable output voltage, for example less than 5% output voltage ripple.
For such applications, surface-mounted components (SMC) are commonly used externally, and connected to a power supply grid at board level, thus providing increased capacitor surface-density.
However, the equivalent serial resistance (ESR) related to the surface-mounted components which are connected to the power supply grid might be significant, due to the long interconnection paths. The same also applies to the equivalent serial inductance, denoted ESL. Therefore, such design appears inadequate for efficient decoupling at high frequency, when high noise rejection is desired.
To overcome this issue, EP 2 145 351 proposes using an integration substrate designed for a system in package, with a through-substrate via and a trench capacitor where the trench is filled with capacitor electrode layers in an alternating arrangement with dielectric layers. The electrode layers are alternatingly connected to a respective one of two capacitor terminals which are provided on the first or second substrate side. The trench capacitor and the through-substrate via are formed in respective trench openings and via openings, in the semiconductor substrate, which have same lateral extent of more than 10 micrometers. This structure allows, among other advantages, a particularly cost-effective fabrication of the integration substrate, because the trench openings and the via openings in the substrate can be fabricated simultaneously.
U.S. Pat. No. 8,283,750 discloses a capacitor structure which is also based on a trench formed in a substrate, with the capacitor layer stack formed in the trench, but the trench is provided with a pillar which extends from the bottom of the trench up to the substrate surface. The capacitor layer stack also covers the sidewalls of the pillar, thereby increasing the capacitor surface-density, and improving the mechanical stability of the integrated circuit obtained. To this end, the pillar sidewalls comprise at least one score or protrusion which extends along the pillar height direction.
Such capacitor structures enable high capacitor surface-density, but they have high values for the equivalent serial resistance, which limits their electrical performances.
From this situation, the present invention aims at providing an alternative solution for decreasing the equivalent serial resistance of capacitor structures while maintaining high capacitor surface-density.
Another object of the invention is to provide capacitor structures which are both reliable and efficient for high-frequency applications, and which are also low-cost for manufacturing.